For many applications, such as system-on-chip (SOC) architecture, it is desirable to integrate logic devices and interface circuits based upon MOS transistors or devices and silicon-oxide-nitride-oxide-semiconductor (SONOS) transistors or devices, on a single chip or substrate to create non-volatile memory (NVM). MOS devices are typically fabricated using a standard or baseline complementary-metal-oxide-semiconductor (CMOS) process flows. SONOS devices include charge-trapping gate stacks in which a stored or trapped charge changes a threshold voltage of the non-volatile memory device to store information as a logic 1 or 0. The integration of these dissimilar devices in SOC architecture is challenging and becomes even more problematic when attempting to form complementary N and P-type SONOS devices with CMOS devices on a single chip or integrated circuit (IC).